Semiconductor light emitting device and manufacturing method of the same

ABSTRACT

According to one embodiment, a semiconductor light emitting device includes a first nitride semiconductor layer, a nitride semiconductor light emitting layer, a second nitride semiconductor layer, a p-side electrode, and an n-side electrode. The nitride semiconductor light emitting layer is provided on the p-side region of the second face of the first nitride semiconductor layer. The second nitride semiconductor layer is provided on the nitride semiconductor light emitting layer. The p-side electrode is provided on the second nitride semiconductor layer. The n-side electrode is provided on the n-side region of the second face of the first nitride semiconductor layer. The nitride semiconductor light emitting layer has a first concave-convex face in a side of the first nitride semiconductor layer, and a second concave-convex face in a side of the second nitride semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2012-103031, filed on Apr. 27, 2012; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor lightemitting device and a manufacturing method of the same.

BACKGROUND

In a light emitting diode (LED), a downsizing of a chip size and anenlargement of a light emitting area are in a trade-off-relationship,and the light emitting area becomes smaller as the downsizing of thechip size makes progress.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a light emitting device ofan embodiment;

FIG. 2 is a schematic enlarged cross sectional view of a semiconductorlayer in FIG. 1;

FIGS. 3A to 16B are schematic views showing a method for manufacturingthe light emitting device of the embodiment;

FIGS. 17A to 17C are schematic views of a light emitting device ofanother specific example of the embodiment;

FIG. 18 is a schematic cross-sectional view of the semiconductor lightemitting device shown in FIG. 17 mounted on a mount substrate;

FIGS. 19A and 19B are schematic cross-sectional views of a lightemitting device of another specific example of the embodiment;

FIGS. 20A and 20B are schematic views showing a method for manufacturinga light emitting device of another embodiment;

FIGS. 21A to 24B are schematic views showing a method for manufacturinga light emitting device of still another embodiment;

FIG. 25 is a schematic cross-sectional view of a light emitting deviceof still another embodiment; and

FIG. 26A and 26B are schematic cross-sectional views of a light emittingdevice of still another embodiment.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor light emitting deviceincludes a first nitride semiconductor layer, a nitride semiconductorlight emitting layer, a second nitride semiconductor layer, a p-sideelectrode, and an n-side electrode. The first nitride semiconductorlayer has a first face and a second face opposite to the first face. Thesecond face has a p-side region and an n-side region. The nitridesemiconductor light emitting layer is provided on the p-side region ofthe second face of the first nitride semiconductor layer. The secondnitride semiconductor layer is provided on the nitride semiconductorlight emitting layer. The p-side electrode is provided on the secondnitride semiconductor layer. The n-side electrode is provided on then-side region of the second face of the first nitride semiconductorlayer. The nitride semiconductor light emitting layer has a firstconcave-convex face in a side of the first nitride semiconductor layer,and a second concave-convex face in a side of the second nitridesemiconductor layer.

A description will be given below of an embodiment with reference to theaccompanying drawings. In this case, in each of the drawings, the samereference numerals are denoted to the same elements.

FIG. 1 is a schematic cross sectional view of a semiconductor lightemitting device 1 according to an embodiment.

FIG. 2 is a schematic enlarged cross sectional view of a semiconductorlayer 15 in the semiconductor light emitting device 1.

The semiconductor light emitting device 1 has a semiconductor layer 15.The semiconductor layer 15 includes a first semiconductor layer 11, asecond semiconductor layer 12, and a light emitting layer 13. The firstsemiconductor layer 11, the second semiconductor layer 12 and the lightemitting layer 13 are all configured by a nitride semiconductorexpressed by In_(x)Al_(y)Ga_(1−x−y)N (0≦x≦1, 0≦y≦1, x+y≦1). In thiscase, it is assumed that a material including an impurity which is addedto control a conductive type is also included in “nitridesemiconductor”.

The first semiconductor layer 11 has a first face 15 a, and a secondface which is provided in an opposite side to the first face 15 a.Further, the second face has a p-side region 14 a and an n-side region14 b. The first semiconductor layer 11 includes, for example, afoundation buffer layer, and an n-type GaN layer.

A light emitting layer (an active layer) 13 is provided on the p-sideregion 14 a in the second face of the first semiconductor layer 11. Thelight emitting layer 13 has, for example, an InGaN group multiplequantum well configuration obtained by stacking plural pairs of an InGaNwell layer and a GaN or an InGaN barrier layer, and emits a blue light,a violet light, a lavender light, an ultraviolet light or the like.

A second semiconductor layer 12 including a p-type GaN layer is providedon the light emitting layer 13. The light emitting layer 13 and thesecond semiconductor layer 12 are not provided in the n-side region 14 bin the second face of the first semiconductor layer 11. In other words,the second face of the first semiconductor layer 11 has the p-sideregion 14 a which is provided with the light emitting layer 13 and thesecond semiconductor layer 12, and the n-side region 14 b which is notprovided with the light emitting layer 13 or the second semiconductorlayer 12, but to which the first semiconductor layer 11 is exposed.

In a plan view in which the second face of the first semiconductor layer11 is seen, a plane area of the p-side region 14 a is wider than a planarea of the n-side region 14 b, and a plane area of the light emittinglayer 13 is wider than the plane area of the n-side region 14 b. The“plane area” in this case is not a surface area, but is an area on aplane facing the second face of the first semiconductor layer 11.

The first face 15 a of the first semiconductor layer 11 serves as a mainpickup face of the light, and the light emitting light of the lightemitting layer 13 is mainly emitted to an outer portion of thesemiconductor layer 15 from the first face 15 a. A p-side electrode 16,an n-side electrode 17 and a support body mentioned later are providedin an opposite side to the first face 15 a.

The first face 15 a of the first semiconductor layer 11 is aconcave-convex face. Also, the p-side region 14 a in the second face ofthe first semiconductor layer 11 is a concave-convex face. The n-sideregion 14 b in the second face is a flat face in an illustration, andmay be a concave-convex face.

As shown in FIG. 2, the light emitting layer 13 is provided in aconformal manner along the concave-convex face in the p-side region 14 ain the second face of the first semiconductor layer 11. Accordingly, thelight emitting layer 13 has a first concave-convex face 13 a in a sideof the first semiconductor layer 11, and a second concave-convex face 13b in a side of the second semiconductor layer 12. The secondsemiconductor layer 12 is provided in a conformal manner along thesecond concave-convex face 13 b of the light emitting layer 13.

The first concave-convex face 13 a and the second concave-convex face 13b of the light emitting layer 13 have a plurality of concave portionsand a plurality of convex portions. One concave portion is formed as aconcave shape, for example, having four triangular side faces of asquare cone as side walls.

A repeating cycle of a plurality of concave portions and convex portionsin the first concave-convex face 13 a and the second concave-convex face13 b is, for example, between 1.4 and 2.1 (μm). A depth of the concaveportion (a height of the convex portion) in the first concave-convexface 13 a and the second concave-convex face 13 b is, for example,between 1.0 and 1.5 (μm).

A p-side electrode 16 is provided on the second semiconductor layer 12.The p-side electrode 16 comes into ohmic contact with the secondsemiconductor layer 12. An n-side electrode 17 is provided in the n-sideregion 14 b in the second surface of the first semiconductor layer 11.The n-side electrode 17 comes into ohmic contact with the firstsemiconductor layer 11.

The p-side electrode 16 and the n-side electrode 17 are provided on thesame face side in an opposite side to the first face 15 a whichcorresponds to a main light pickup face in the semiconductor layer 15,the p-side electrode 16 is provided on a region which includes the lightemitting layer 13, and the n-side electrode 17 is provided on a regionwhich does not include the light emitting layer 13.

The second semiconductor layer 12 is formed in a conformal manner alongthe concave-convex shape of the light emitting layer 13. Accordingly, aface in an opposite side to the light emitting layer 13 in the secondsemiconductor layer 12 is a concave-convex face, and a contact facebetween the second semiconductor layer 12 and the p-side electrode 16 isan concave-convex face.

The n-side region 14 b in the second face of the first semiconductorlayer 11 is formed such that the face of the first semiconductor layer11 is exposed, by selectively removing the light emitting layer 13 whichis formed on a whole face of the second face of the first semiconductorlayer 11, and a part of the second semiconductor layer 12, as mentionedlater. The n-side region 14 b may be a case that it is a concave-convexface, or a case that it is a flat face. Accordingly, the contact facebetween the first semiconductor layer 11 and the n-side electrode 17 maybe a concave-convex face or a flat face.

FIG. 8B illustrates a plan view of a face on which is provided with thep-side electrode 16 and the n-side electrode 17, and an area of thep-side electrode 16 is wider than an area of the n-side electrode 17 onthe plan view. In this case, a layout of the p-side electrode 16 and then-side electrode 17 shown in FIG. 8B is an example, and is not limitedto this.

A first insulating film (hereinafter, refer simply to as an insulatingfilm) 18 is provided on the faces other than the first face 15 a in thesemiconductor layer 15. The insulating film 18 covers the n-side region14 b of the first semiconductor layer 11, the face of the secondsemiconductor layer 12, the side face of the second semiconductor layer12, the side face of the light emitting layer 13, the p-side electrode16 and the n-side electrode 17.

In this case, another insulating film (for example, a silicon oxidefilm) may be provided between the insulating film 18 and thesemiconductor layer 15. The insulating film 18 is a resin, for example,a polyimide or the like which is excellent in a patterning property of afine opening. Alternatively, an inorganic film such as a silicon oxidefilm, a silicon nitride film or the like may be used as the insulatingfilm 18.

The insulating film 18 is not provided on the first face 15 a of thesemiconductor layer 15. The insulating film 18 covers and protects theside face 15 c which comes from the first face 15 a in the firstsemiconductor layer 11.

A p-side interconnection layer 21 and an n-side interconnection layer 22are provided on a surface in an opposite side to the semiconductor layer15 so as to be spaced from each other.

The p-side interconnection layer 21 is provided within a plurality offirst openings 18 a which reach the p-side electrode 16 and are formedin the insulating film 18, and is electrically connected to the p-sideelectrode 16. The n-side interconnection layer 22 is formed within asecond opening 18 b which reaches the n-side electrode 17 and is formedin the insulating film 18, and is electrically connected to the n-sideelectrode 17.

A p-side metal pillar 23 is provided in a face in an opposite side tothe p-side electrode 16 in the p-side interconnection layer 21. Thep-side interconnection layer 21, the p-side metal pillar 23 and themetal film 19 which is used as a seed layer mentioned later configurethe p-side interconnection portion in the embodiment.

An n-side metal pillar 24 is provided in a face in an opposite side tothe n-side electrode 17 in the n-side interconnection layer 22. Then-side interconnection layer 22, the n-side metal pillar 24, and themetal film 19 which is used as the seed layer mentioned later configurethe n-side interconnection portion in the embodiment.

For example, a resin layer 25 is stacked as a second insulating film onthe insulating film 18. The resin layer 25 covers a periphery of thep-side interconnection portion and a periphery of the n-sideinterconnection portion. Further, the resin layer 25 is filled betweenthe p-side metal pillar 23 and the n-side metal pillar 24.

The side face of the p-side metal pillar 23 and the side face of then-side metal pillar 24 are covered by the resin layer 25. A face in anopposite side to the p-side interconnection layer 21 in the p-side metalpillar 23 is exposed from the resin layer 25, and serves as a p-sideouter terminal 23 a. A face in an opposite side to the n-sideinterconnection layer 22 in the n-side metal pillar 24 is exposed fromthe resin layer 25 and serves as an n-side outer terminal 24 a.

The p-side outer terminal 23 a and the n-side outer terminal 24 a arebonded to a pad which is formed in a mounting substrate, via a bondingmaterial such as a solder, the other metals, a conductive material orthe like.

A distance between the p-side outer terminal 23 a and the n-side outerterminal 24 a which are exposed on the same face (the lower face inFIG. 1) in the resin layer 25 is larger than a distance between thep-side interconnection layer 21 and the n-side interconnection layer 22on the insulating film 18. The p-side outer terminal 23 a and the n-sideouter terminal 24 a are spaced at a distance at which they are not shortcircuited with each other by the solder or the like at a time of beingmounted to the mounting substrate.

The p-side interconnection layer 21 can be moved close to the n-sideinterconnection layer 22 to a critical limit on a process, and it ispossible to widen an area of the p-side interconnection layer 21. As aresult, it is possible to achieve an enlargement of a contact facebetween the p-side interconnection layer 21 and the p-side electrode 16,and it is possible to improve a current distribution and a heatradiating property.

An area by which the p-side interconnection layer 21 comes into contactwith the p-side electrode 16 through a plurality of first openings 18 ais larger than an area by which the n-side interconnection layer 22comes into contact with the n-side electrode 17 through the secondopening 18 b. Accordingly, a current distribution to the light emittinglayer 13 is improved, and a heat radiating property of the lightemitting layer 13 can be improved.

An area of the n-side interconnection layer 22 expanding on theinsulating film 18 is larger than an area by which the n-sideinterconnection layer 22 comes into contact with the n-side electrode17.

In accordance with the embodiment, it is possible to obtain a high lightoutput by the light emitting layer 13 which is formed over a widerregion than the n-side electrode 17. In this case, the n-side electrode17 which is provided in a narrower region than the region which includesthe light emitting layer 13 is drawn out as the n-side interconnectionlayer 22 having a greater area to the mounting face side.

The first semiconductor layer 11 is electrically connected to the n-sidemetal pillar 24 which has the n-side outer terminal 24 a, via the n-sideelectrode 17, the metal film 19 and the n-side interconnection layer 22.The second semiconductor layer 12 is electrically connected to thep-side metal pillar 23 which has the p-side outer terminal 23 a, via thep-side electrode 16, the metal film 19 and the p-side interconnectionlayer 21.

The p-side metal pillar 23 is thicker than the p-side interconnectionlayer 21, and the n-side metal pillar 24 is thicker than the n-sideinterconnection layer 22. A thickness of each of the p-side metal pillar23, the n-side metal pillar 24 and the resin layer 25 is thicker thanthe semiconductor layer 15. In this case, “thickness” in this caserefers to a thickness in a vertical direction in FIG. 1.

Further, a thickness of each of the p-side metal pillar 23 and then-side metal pillar 24 is thicker than a thickness of a stacked bodywhich includes the semiconductor layer 15, the p-side electrode 16, then-side electrode 17 and the insulating film 18. In this case, an aspectratio (a ratio of a thickness with respect to a plane size) of each ofthe metal pillars 23 and 24 is not limited to be not Tess than 1, butalso may be smaller than 1. In other words, the metal pillars 23 and 24may be configured such that the thickness is smaller than the planesize.

In accordance with the embodiment, even if the substrate 10 which isused for forming the semiconductor layer 15 and is mentioned later isremoved, it is possible to stably support the semiconductor layer 15 bya support body which includes the p-side metal pillar 23, the n-sidemetal pillar 24 and the resin layer 25, and it is possible to enhance amechanical strength of the semiconductor light emitting device 1.

As the material of the p-side interconnection layer 21, the n-sideinterconnection layer 22, the p-side metal pillar 23 and the n-sidemetal pillar 24, a copper, a gold, a nickel, a silver and the like canbe used. Among them, if the copper is used, it is possible to obtain agood heat conductivity, a high migration resistance and an excellentadhesion to the insulating material.

The resin layer 25 reinforces the p-side metal pillar 23 and the n-sidemetal pillar 24. It is desirable that the resin layer 25 employs aconfiguration in which a coefficient of thermal expansion is the same asor similar to the mounting substrate. As the resin layer 25 mentionedabove, there can be listed up, for example, an epoxy resin, a siliconeresin, a fluorocarbon resin and the like.

Further, in a state in which the semiconductor light emitting device 1is mounted to the mounting substrate via the p-side outer terminal 23 aand the n-side outer terminal 24 a, it is possible to reduce a stresswhich is applied to the semiconductor layer 15 via the solder or thelike, by allowing the p-side metal pillar 23 and the n-side metal pillar24 to absorb the stress.

The p-side interconnection portion which includes the p-sideinterconnection layer 21 and the p-side metal pillar 23 is connected tothe p-side electrode 16 via a plurality of vias 21 a which are providedwithin a plurality of first openings 18 a and are segmented from eachother. Accordingly, a high stress reducing effect by the p-sideinterconnection portion can be obtained.

Alternatively, as shown in FIG. 19A, the p-side interconnection layer 21may be connected to the p-side electrode 16 via a post 21 c which isprovided within one large first opening 18 a and is larger in a planesize than the via 21 a. In this case, it is possible to achieve animprovement of a heat radiating property of the light emitting layer 13through the p-side electrode 16, the p-side interconnection layer 21 andthe p-side metal pillar 23 which are all made of metal.

As mentioned later, the substrate 10 which is used at a time of formingthe semiconductor layer 15 is removed from the first face 15 a.Accordingly, it is possible to make a back of the semiconductor lightemitting device 1 low.

A phosphor layer 30 is provided on the first face 15 a. The phosphorlayer 30 has a transparent resin 31, and a plurality of granularphosphor 32 which are dispersed into the transparent resin 31.

The transparent resin 31 has a permeability with respect to the lightemitting light of the light emitting layer 13 and the light emittinglight of the phosphor 32, and can employ, for example, a silicone resin,an acrylic resin, a phenyl resin or the like.

The phosphor 32 can absorb the light emitting light (the excited light)of the light emitting layer 13, and emit a wavelength converting light.Accordingly, the semiconductor light emitting device 1 can emit a mixedlight of the light emitting light of the light emitting layer 13 and thewavelength converting light of the phosphor 32.

For example, if the phosphor 32 is a yellow phosphor which emits ayellow light, it is possible to obtain a white color or an electric lampcolor as a mixed color of a blue color of the light emitting layer 13serving as an InGaN material, and a yellow light serving as thewavelength converting light in the phosphor 32. In this case, thephosphor layer 30 may be configured such as to include plural kinds ofphosphors (for example, a red phosphor which emits a red light, and agreen phosphor which emits a green light).

In accordance with the embodiment described above, the light emittinglayer 13 is provided as not a flat film but a film having aconcave-convexity. Accordingly, in the case of comparing within the sameplane size, the surface area of the light emitting layer 13 can beincreased more than that case that it is provided as the flat film, andit is possible to increase an effective light emitting area of the lightemitting layer 13. As a result, it is possible to suppress a reductionof the light emitting area while achieving a downsizing and a costreduction on the basis of a reduction of a chip size, and a highefficiency can be realized even in a small chip size.

Next, a description will be given of a manufacturing method of thesemiconductor light emitting device 1 of the embodiment, with referenceto FIG. 3A to FIG. 16B. FIG. 3A to FIG. 16B show a partial region in awafer state.

The semiconductor layer 15 is epitaxial grown on the substrate 10 whichis the silicon substrate. In the embodiment, a buffer layer whichreduces a lattice constant difference between the silicon substrate andthe semiconductor layer 15 is included in the semiconductor layer 15.

First of all, as shown in FIG. 3A, a mask 93 is formed on a whole faceof the main face 10 a of the substrate 10. The main face 10 a is a (100)face of the silicon substrate. The mask 93 is, for example, a siliconoxide film.

On the mask 93, a plurality of openings 93 a are selectively formed, asshown in FIG. 3B, in accordance with a lithography and an etching, forexample, using a hydrofluoric acid. A plane shape of the opening 93 a isquadrangular. The main face 10 a of the substrate 10 is exposed to theopening 93 a.

Further, a wet etching is carried out using the mask 93 on which theopening 93 a is formed. As an etching fluid, for example, an alkaliliquid such as a potassium hydroxide (KOH) or the like can be used.

The etching is a crystalline anisotropic etching of a silicon whichutilizes a difference in an etching speed by a crystal face of thesilicon. A (111) face in the silicon is harder to be etched than the(100) face, with respect to the alkaline etching fluid (the etchingspeed is low).

In other words, if the main face 10 a of the substrate 10 in which aface direction is the (100) face is etched, the (111) face 10 b which isinclined with respect to the main face 10 a appears as shown in FIG. 3C.Thereafter, the mask 93 is removed by, for example, the hydrofluoricacid (FIG. 3D). A schematic plan view of the state is shown in FIG. 4.

In accordance with the crystalline anisotropic etching of the siliconmentioned above, concavities and convexities including a plurality ofconcave portions .5 are formed on the substrate 10. One concave portion5 has four triangular (111) faces 10 b which have a common apex in abottom portion of the concave portion 5, as a side wall, as shown inFIG. 4.

The semiconductor layer 15 represented by In_(x)Al_(y)Ga_(1−x−y)N(0≦x≦1, 0≦y≦1, x+y≦1) can be made less in its defect than the othercrystal face in the silicon and can be epitaxial grown to the (111) face10 b.

As shown in FIG. 3E, the first semiconductor layer 11 is formed on theconcave-convex face of the substrate 10, the light emitting layer 13 isformed on the first semiconductor layer 11, and the second semiconductorlayer 12 is formed on the light emitting layer 13.

The first semiconductor layer 11, the light emitting layer 13 and thesecond semiconductor layer 12 are all formed in a conformal manner alongthe concave-convex face of the substrate 10. Accordingly, a plurality ofconcave portions which are formed as a similar or close shape to aplurality of concave portions 5 shown in FIG. 4 formed in the substrate10 are formed in the light emitting layer 13 in a plan view in which thelight emitting layer 13 from the second semiconductor layer 12 side isseen.

As mentioned above, according to the embodiment, the surface area of thelight emitting layer 13 is increased rather, than formed as the flatfilm, by forming the concavities and convexities in the substrate 10 andforming the semiconductor layer 15 including the light emitting layer 13in a conformal manner along the concavities and convexities, whereby itis possible to expand an effective light emitting area.

On the basis of a control of an etching condition such as an etchingtime or the like, an upper end of the convex portion in the concavitiesand convexities of the substrate 10 can be formed as an acute shape, asshown in FIG. 20A.

Further, FIG. 20B shows a configuration in which the flat face 10 cserving as the same face direction (100) face as the main face of thesubstrate 10 is formed in the bottom of the concave portion 5. Anopening pitch of the mask 93 in FIG. 20B is larger than the openingpitch of the mask 93 in FIG. 3B mentioned above. The first face 15 a ofthe semiconductor layer 15 which is formed on the substrate 10 shown inFIG. 20B is a concave-convex shape including a convex portion in whichan upper end is flat.

FIG. 5A is a schematic cross sectional view which corresponds to FIG.3E, and FIG. 5B corresponds to a bottom elevational view in FIG. 5A.

After forming the semiconductor layer 15 in a whole face of thesubstrate 10, a groove 80 which reaches the substrate 10 through thesemiconductor layer 15 is formed as shown in FIG. 6A and FIG. 6Bcorresponding to a bottom elevational view thereof, for example, inaccordance with a reactive ion etching (RIE) method using a resist whichis not illustrated. The groove 80 is formed, for example, as a latticeshape on the substrate 10 in the wafer state, and separates thesemiconductor layer 15 into a plurality of chips on the substrate 10.

In this case, a process of separating the semiconductor layer 15 into aplurality of sections may be carried out after selectively removing thesecond semiconductor layer 12 mentioned later or forming the electrode.

Next, the light emitting layer 13 and a part of the second semiconductorlayer 12 are removed, and a part of the first semiconductor layer 11 isexposed, as shown in FIG. 7A and FIG. 7B corresponding to a bottomelevational view thereof, for example, in accordance with the RIE methodusing the resist which is not illustrated. A region in which the firstsemiconductor layer 11 is exposed is the n-side region 14 b which doesnot include the light emitting layer 13.

Next, as shown in FIG. 8A and FIG. 8B corresponding to a bottomelevational view thereof, the p-side electrode 16 is formed on thesurface of the second semiconductor layer 12, and the n-side electrode17 is formed on the exposed face of the first semiconductor layer 11.

The p-side electrode 16 and the n-side electrode 17 are formed, forexample, in accordance with a sputter method, a vapor deposition methodor the like. Whichever of the p-side electrode 16 and the n-sideelectrode 17 may be formed in advance, or they may be formedsimultaneously by the same material.

The p-side electrode 16 includes, for example, a silver, a silver alloy,an aluminum, an aluminum alloy or the like which has a reflectingproperty with respect to the light emitting light of the light emittinglayer 13. Further, in order to prevent a sulfuration and an oxidation ofthe p-side electrode 16, it may be configured such as to include a metalprotecting film (a barrier metal).

Further, for example, a silicon nitride film or a silicon oxide film maybe formed in accordance with a chemical vapor deposition (CVD) method,as a passivation film between the p-side electrode 16 and the n-sideelectrode 17, or on the end face (the side face) of the light emittinglayer 13. Further, an activation anneal or the like for obtaining anohmic contact between each of the electrodes and the semiconductor layermay be executed as appropriate.

Next, after covering all the exposed portion on the substrate 10 by theinsulating film 18 shown in FIG. 9A, the insulating film 18 ispatterned, for example, in accordance with the wet etching, and thefirst opening 18 a and the second opening 18 b are formed selectively inthe insulating film 18. The first opening 18 a reaches the p-sideelectrode 16. The second opening 18 b reaches the n-side electrode 17.

The concavities and convexities which reflect the concavities andconvexities of the substrate 10 are formed on the contact face with thesubstrate 10 in the insulating film 18.

As the insulating film 18, for example, there can be employed an organicmaterial such as a photosensitive polyimide, a benzocyclobutene or thelike. In this case, it is possible to directly expose and develop withrespect to the insulating film 18 without using any resist.

Alternatively, an inorganic film such as a silicon nitrogen film, asilicon oxide film or the like may be used as the insulating film 18. Inthe case that the insulating film 18 is the inorganic film, the firstopening 18 a and the second opening 18 b are formed by an etching afterpatterning the resist which is formed on the insulating film 18.

Next, the metal film 19 is formed, as shown in FIG. 9B, on the surfaceof the insulating film 18, the inner wall (the side wall and the bottomportion) of the first opening 18 a, and the inner wall (the side walland the bottom portion) of the second opening 18 b. The metal film 19 isused as a seed metal for plating mentioned later.

The metal film 19 is formed, for example, in accordance with the sputtermethod. The metal film 19 includes, for example, a stacked film of atitanium (Ti) and a copper (Cu) which are stacked in this order from theinsulating film 18 side. Alternatively, an aluminum film may be used inplace of the titanium film.

Next, as shown in FIG. 9C, a resist 91 is selectively formed on themetal film 19, and a Cu electrolyte plating using the metal film 19 as acurrent route is carried out.

Accordingly, as shown in FIG. 10A and FIG. 10B corresponding to a bottomelevational view thereof, the p-side interconnection layer 21 and then-side interconnection layer 22 are selectively formed on the metal film19. The p-side interconnection layer 21 and the n-side interconnectionlayer 22 are formed simultaneously in accordance with a plating methodand are made, for, example, of a cupper material.

The p-side interconnection layer 21 is formed within the first opening18 a, and is electrically connected to the p-side electrode 16 via themetal film 19. The n-side interconnection layer 22 is formed within thesecond opening 18 b, and is electrically connected to the n-sideelectrode 17 via the metal film 19.

The resist 91 which is used for plating the p-side interconnection layer21 and the n-side interconnection layer 22 is removed using solvent oran oxygen plasma.

Next, as shown in FIG. 11A and FIG. 11B corresponding to a bottomelevational view thereof, a resist 92 for forming the metal pillar isformed. The resist 92 is thicker than the resist 91 mentioned above. Inthis case, the resist 91 may be left without being removed in thepreceding process, and the resist 92 may be formed in an overlappingmanner with the resist 91. A first opening 92 a and a second opening 92b are formed in the resist 92.

Further, a Cu electrolyte plating in which the metal film 19 is set tothe current route is carried out using the resist 92 as a mask.Accordingly, as shown in FIG. 12A and FIG. 12B corresponding to a bottomelevational view thereof, the p-side metal pillar 23 and the n-sidemetal pillar 24 are formed.

The p-side metal pillar 23 is formed on the surface of the p-sideinterconnection layer 21 within the first opening 92 a which is formedin the resist 92. The n-side metal pillar 24 is formed on the surface ofthe n-side interconnection layer 22 within the second opening 92 b whichis formed in the resist 92. The p-side metal pillar 23 and the n-sidemetal pillar 24 are formed simultaneously in accordance with the platingmethod, and is made, for example, of a cupper material.

The resist 92 is removed, for example, using the solvent or the oxygenplasma, as shown in FIG. 13A. Thereafter, the exposed portion of themetal film 19 is removed in accordance with the wet etching, by settingthe metal pillar 23, the n-side metal pillar 24, the p-sideinterconnection layer 21 and the n-side interconnection layer 22 to amask. Accordingly, as shown in FIG. 13B, the electric connection via themetal film 19 between the p-side interconnection layer 21 and the n-sideinterconnection layer 22 is segmented.

Next, as shown in FIG. 14A, the resin layer 25 is stacked with respect,to the insulating film 18. The resin layer 25 covers the p-sideinterconnection layer 21, the n-side interconnection layer 22, thep-side metal pillar 23 and the n-side metal pillar 24.

The resin layer 25 has an insulating property. Further, the resin layer25 may be included, for example, by a carbon black, and a lightinsulating property may be applied to the light emitting light of thelight emitting layer 13.

Next, as shown in FIG. 14B, the substrate 10 is removed. The substrate10 corresponding to the silicon substrate can be removed by an etching.

Since the above-mentioned stacked body which is formed on the substrate10 is reinforced by the p-side metal pillar 23, the n-side metal pillar24 and the resin layer 25 which are thicker than the semiconductor layer15, the wafer state can be maintained even if the substrate 10 runsshort.

Further, the resin layer 25, and the metal configuring the p-side metalpillar 23 and the n-side metal pillar 24 are a more flexible material incomparison with the semiconductor layer 15. The semiconductor layer 15is supported by the flexible support body mentioned above. Accordingly,even if a great internal stress which is generated at a time ofepitaxial growing the semiconductor layer 15 on the substrate 10 isreleased at a stroke at a time of removing the substrate 10, it ispossible to avoid the breakage of the semiconductor layer 15.

The first face 15 a of the semiconductor layer 15 from which thesubstrate 10 is removed, shown in FIG. 15A is washed. The gallium (Ga)attached to the first face 15 a is removed, for example, by a dilutedhydrofluoric acid or the like.

Next, as shown in FIG. 15B, the phosphor layer 30 is formed on the firstface 15 a. The phosphor layer 30 is formed on the insulating film 18between the adjacent semiconductor layers 15.

The liquid transparent resin 31 in which the phosphor 32 is dispersed issupplied onto the first face 15 a, for example, in accordance with aprinting method, a potting method, a molding method, a compressionforming method or the like, and is thereafter hardened.

Next, a surface (a lower face in FIG. 15B) of the resin layer 25 isground, and the p-side outer terminal 23 a and the n-side outer terminal24 a are exposed, as shown in FIG. 16A and FIG. 16B corresponding to abottom elevational view thereof.

Thereafter, the phosphor layer 30, the insulating film 18 and the resinlayer 25 are cut at a position of the groove 80 mentioned above, and aresegmented into a plurality of semiconductor light emitting devices 1.For example, they are cut using a dicing blade. Alternatively, they maybe cut with a laser irradiation.

The substrate 10 has been already removed at a time of dicing. Further,since the semiconductor layer 15 does not exist in the groove 80, it ispossible to avoid a damage to which the semiconductor layer 15 isexposed at a time of dicing. Further, without any additional processafter being segmented, it is possible to obtain a configuration in whichthe end portion (the side face) of the semiconductor layer 15 is coveredand protected by the insulating film 18.

In this case, the segmented semiconductor light emitting device 1 may beformed as a single chip configuration which includes one semiconductorlayer 15 or may be formed as a multiple chip configuration whichincludes a plurality of semiconductor layers 15.

Since each of the processes mentioned above before dicing is carried outin a lump in the wafer state, it is not necessary to carry out ainterconnection and a packaging per the segmented individual device, andit is possible to widely reduce a production cost. In other words, theinterconnection and the packaging have been already carried out in thesegmented state. Accordingly, it is possible to enhance a productivity.As a result, it is easy to reduce a cost.

On the first surface 15 a, a lens 36 may be provided such as asemiconductor light emitting device 2 shown in FIGS. 17A to 17C and FIG.18. The lens 36 is not limited to be formed as a concave shape, but maybe formed as a convex shape.

FIG. 17A is a schematic perspective view of the semiconductor lightemitting device 2 of a variation of the embodiment. FIG. 17B is a crosssectional view along a line A-A in FIG. 17A. FIG. 17C is a crosssectional view along a line B-B in FIG. 17A.

FIG. 18 is a schematic cross sectional view of a light emitting modulehaving a configuration in which the semiconductor light emitting device2 is mounted on a mounting substrate 200.

As shown in FIGS. 17A and 17C, a side face of a part of the p-side metalpillar 23 is a third face 25 b having a different face direction fromthe first face 15 a and the second face of the semiconductor layer 15,and is exposed from the resin layer 25. The exposed face serves as thep-side outer terminal 23 b for mounting to the mounting substrate in anouter portion.

The third face 25 b is a face which is approximately vertical to thefirst face 15 a and the second face of the semiconductor layer 15. Theresin layer 25 has four side faces, for example, formed as a rectangularshape, and one of the side faces is the third face 25 b.

In the same third face 25 b, a side face of a part of the n-side metalpillar 24 is exposed from the resin layer 25. The exposed face serves asthe n-side outer terminal 24 b for mounting to the mounting substrate inthe outer portion.

Further, as shown in FIG. 17A, the side face 21 b of a part of thep-side interconnection layer 21 is exposed from the resin layer 25 inthe third face 25 b, and serves as the p-side outer terminal. In thesame manner, the side face 22 b of a part of the n-side interconnectionlayer 22 is exposed from the resin layer 25 in the third face 25 b, andserves as the n-side outer terminal.

In the p-side metal pillar 23, the portions other than the p-side outerterminal 23 b which are exposed in the third face 25 b are covered bythe resin layer 25. Further, in the n-side metal pillar 24, the portionsother than the n-side outer terminal 24 b which are exposed in the thirdface 25 b are covered by the resin layer 25.

Further, in the p-side interconnection layer 21, the portions other thanthe side face 21 b which are exposed in the third face 25 b are coveredby the resin layer 25. Further, in the n-side interconnection layer 22,the portions other than the side face 22 b which are exposed in thethird face 25 b are covered by the resin layer 25.

The semiconductor light emitting device 2 is mounted in such a manner inwhich the third face 25 b is directed to a mounting face 201 of themounting substrate 200, as shown in FIG. 18. Each of the p-side outerterminal 23 b and the n-side outer terminal 24 b which are exposed inthe third face 25 b is bonded to a pad. 202 which is formed in themounting face 201 via a solder 203. A interconnection pattern is formedin the mounting face 201 of the mounting substrate 200, and the pad 202is connected to the interconnection pattern.

The third face 25 b is approximately vertical to the first face 15 awhich is a main emitting face of the light. Accordingly, in such amanner in which the third face 25 b is directed downward to the mountingface 201 side, the first face 15 a is directed not to above the mountingface 201 but to a transverse direction. In other words, thesemiconductor light emitting device 2 is a so-called side view typesemiconductor light emitting device in which the light is discharged inthe transverse direction in the case that the mounting face 201 is ahorizontal face.

Further, FIG. 19B is a schematic cross sectional view of a semiconductorlight emitting device 3 according to the other variation of theembodiment.

In the semiconductor light emitting device 3 shown in FIG. 19B, a p-sidepad 51 which covers the p-side electrode 16 is provided on a surface anda side face of the p-side electrode 16. The p-side electrode 16includes, for example, at least one of a nickel (Ni), a gold (Au) and arhodium (Rh) which can form an alloy with the gallium (Ga) included inthe semiconductor layer 15. The p-side pad 51 is higher in a reflectancewith respect to the light emitting light of the light emitting layer 13than the p-side electrode 16, and includes, for example, the silver (Ag)as a main component. Further, the p-side pad 51 protects the p-sideelectrode 16 from an oxidation and a corrosion.

Further, an n-side pad 52 which covers the n-side electrode 17 isprovided on a surface and a side face of the n-side electrode 17. Then-side electrode 17 includes, for example, at least one of the nickel(Ni), the gold (Au) and the rhodium (Rh) which can form the alloy withthe gallium (Ga) included in the semiconductor layer 15. The n-side pad52 is higher in a reflectance with respect to the light emitting lightof the light emitting layer 13 than the n-side electrode 17, andincludes, for example, the silver (Ag) as a main component. Further, then-side pad 52 protects the n-side electrode 17 from an oxidation and acorrosion.

An insulating film 53, for example, a silicon oxide film, a siliconnitride film or the like is provided in a periphery of the p-sideelectrode 16 and a periphery of the n-side electrode 17 in a face in anopposite side to the first face 15 a in the semiconductor layer 15. Theinsulating film 53 is provided between the p-side electrode 16 and then-side electrode 17, and between the p-side pad 51 and the n-side pad52.

An insulating film 54, for example, a silicon oxide film, a siliconnitride film or the like is provided on the insulating film 53, on thep-side pad 51 and on the n-side pad 52. Further, the insulating film 54is provided on the side face 15 c of the semiconductor layer 15, andcovers the side face 15 c.

The p-side interconnection layer 21 and the n-side interconnection layer22 are provided on the insulating film 54. The p-side interconnectionlayer 21 is connected to the p-side pad 51 through a first opening 54 awhich is formed in the insulating film 54. The n-side interconnectionlayer 22 is connected to the n-side pad 52 through a second opening 54 bwhich is formed in the insulating film 54.

In the configuration, the p-side interconnection layer 21 may beconnected to the p-side pad 51 via a plurality of vias 21 a as shown inFIG. 19B, or may be connected to the p-side pad 51 via one post in whicha plane size is larger than the via 21 a.

The p-side metal pillar 23 which is thicker than the p-sideinterconnection layer 21 is provided on the p-side interconnection layer21. The n-side metal pillar 24 which is thicker than the n-sideinterconnection layer 22 is provided on the n-side interconnection layer22.

The resin layer 25 is stacked with respect to the insulating film 54.The resin layer 25 covers the p-side interconnection portion whichincludes the p-side interconnection layer 21 and the p-side metal pillar23, and the n-side interconnection portion which includes the n-sideinterconnection layer 22 and the n-side metal pillar 24. In this case, aface (a lower face in the drawing) in an opposite side to the p-sideinterconnection layer 21 in the p-side metal pillar 23 is exposed fromthe resin layer 25, and serves as the p-side outer terminal 23 a. In thesame manner, a face (a lower face in the drawing) in an opposite side tothe n-side interconnection layer 22 in the n-side metal pillar 24 isexposed from the resin layer 25, and serves as the n-side outer terminal24 a.

Alternatively, the side face of the p-side metal pillar 23 and the sideface of the n-side metal pillar 24 may be exposed, so as to be a sideview type semiconductor light emitting device.

The resin layer 25 is filled into the groove 80 mentioned above whichseparates the semiconductor layer 15 into a plurality of sections on thesubstrate 10, via the insulating film 54. Accordingly, the side face 15c of the semiconductor layer 15 is covered and protected by theinsulating film 54 which is the inorganic film, and the resin layer 25.

In accordance with the embodiment, a concave-convexity process ispreviously applied to the substrate 10 for growing the semiconductorlayer 15. The concave-convexity process with respect to the substrate 10which is the silicon substrate is easily carried out.

Further, the semiconductor layer 15 is formed on the concave-convex faceof the substrate 10. Accordingly, after removing the substrate 10, theface (the first face 15 a) which is in contact with the substrate 10 inthe semiconductor layer 15 is the concave-convex face. Accordingly, aroughening process which enhances a light pickup efficiency, afterremoving the substrate, is eliminated. Further, it is possible to reducean efficiency reduction due to a damage (a deterioration) at a time ofthe roughening process of the semiconductor layer 15.

In some process depth of the concavities and convexities of thesubstrate 10, and some film thickness of the semiconductor layer 15which is formed on the concave-convex face, as shown in FIG. 21A, thelight emitting layer 13 and the second semiconductor layer 12 can beformed as the flat film without generating any concavities andconvexities.

Even in this case, the concavities and convexities which reflect theconcavities and convexities of the substrate 10 are formed on the firstface 15 a which is the light pickup face. In other words, in the samemanner as mentioned above, if the substrate 10 is removed after formingthe electrodes 16 and 17, the insulating film 18, the interconnectionlayers 21 and 22, the metal pillars 23 and 24, the resin layer 25 andthe like, the first face 15 a which is the concave-convex face isexposed, as shown in FIG. 21B. Accordingly, there can be obtained aconfiguration in which the light pickup efficiency is enhanced withoutcarrying out the roughening process after removing the substrate.Further, it is possible to prevent an efficiency reduction due to thedamage (the deterioration) at a time of the roughening process of thesemiconductor layer 15.

Next, FIGS. 22A to 22E are schematic cross sectional views which show amanufacturing method of a semiconductor light emitting device of stillanother embodiment.

As shown in FIG. 22A, the semiconductor layer 15 is formed on a mainface of the substrate 10 via an aluminum nitride (AlN) film 8. Thesubstrate 10 is not limited to the silicon substrate, but may be asapphire substrate. The AlN film 8 serves as a buffer layer whichreduces a lattice unconformity between the substrate 10 and the GaNsemiconductor layer 15. The main face of the substrate 10 is not formedas the concavities and convexities, and the AlN film 8 is formed on aflat face.

The buffer layer is not limited to the AlN film, but can employ asilicon nitride film (a SiN film), a silicon oxynitride film (a SiONfilm), a silicon oxide film including a carbon (a SiOC film), and asilicon carbide film (a SiC film).

After forming the semiconductor layer 15, the p-side electrode and then-side electrode are formed in the semiconductor layer 15 in the samemanner as the embodiment mentioned above, and the support body includingthe interconnection layer, the metal pillar and the resin layer isformed in an opposite side to the substrate 10. Further, after formingthe support body, the substrate 10 is removed.

The AlN film 8 is exposed by removing the substrate 10. A resist 94 isformed and patterned on the AlN film 8, as shown in FIG. 22B.

Further, the AlN film 8 is processed, for example, in accordance withthe RIE method using a BCl₃ gas, as shown in FIG. 22C, by setting thepatterned resist 94 to a mask. Further, the GaN semiconductor layer 15is subsequently processed in accordance with the RIE method whileleaving the resist 94. Alternatively, the semiconductor layer 15 can beprocessed in accordance with a wet process which uses a potassiumhydroxide (KOH), a tetramethylammonium hydroxide (TMAH) or the like.

Accordingly, as shown in FIG. 22D, the concavities and convexities areformed on the surface (the first face) of the semiconductor layer 15. Ata time of processing the semiconductor layer 15, the AlN film 8 is notcompletely removed, but is partly left in an upper end (a top portion)of the convex portion of the semiconductor layer 15.

Thereafter, the resist 94 is removed in accordance with an ashing methodwhich uses an oxygen (FIG. 22E). In accordance with the embodiment,there can be obtained a configuration in which the concavities andconvexities are formed on the light pickup face (the first face) of thesemiconductor layer 15, and the AlN film 8 is provided in the upper end(the top portion) of the convex portion in the concave-convex face ofthe semiconductor layer 15. The AlN film 8 is not provided in theconcave portion in the concave-convex face of the semiconductor layer15, but the AlN film 8 is selectively provided only in the upper end(the top portion) of the convex portion.

The AlN film 8 having a different refraction index from the GaN materialof the light pickup face exists in the light pickup face of thesemiconductor layer 15. Accordingly, it is possible to suppress a colorbreakup and improve the light pickup efficiency, on the basis of a lightscattering effect by the AlN film 8. Further, since the AlN film 8exists in the light pickup surface, a roughened shaped of the lightpickup face becomes stable, and it is possible to improve a light pickupefficiency.

As the buffer layer, the materials mentioned above can be employed inaddition to the AlN film. Even in the case that the materials other thanthe AlN film are used as the buffer layer, there is provided aconfiguration in which a film (a SiN film, a SiON film, an SiOC film ora SiC film) of a material having a different refraction index from theGaN semiconductor layer 15 is provided in the upper end (the topportion) of the convex portion of the first face of the semiconductorlayer 15. Even in this case, it is possible to suppress the colorbreakup and improve the light pickup efficiency on the basis of thelight scattering effect by the film.

FIG. 25 is a schematic cross sectional view of a semiconductor lightemitting device in which a film (for example, exemplified by the AlNfilm 8) having the different refraction index from the semiconductorlayer 15 is provided in the upper end (the top portion) of the convexportion in the concavities and convexities of the first face 15 a.

In a face in an opposite side to the first face 15 a in thesemiconductor layer 15, in the same manner as the embodiment mentionedabove, the p-side electrode 16 and the n-side electrode 17 are provided.Further, the insulating film 18 which covers the p-side electrode 16 andthe n-side electrode 17 is provided in an opposite side to the firstface 15 a, and the p-side interconnection layer 21 which is connected tothe p-side electrode 16, and the n-side interconnection layer 22 whichis connected to the n-side electrode 17 are provided on the insulatingfilm 18. The p-side metal pillar 23 is provided on the p-sideinterconnection layer 21, and the n-side metal pillar 24 is provided onthe n-side interconnection layer 22. The resin layer 25 is provided inthe periphery of the p-side metal pillar 23 and the periphery of then-side metal pillar 24.

In the semiconductor layer 15 shown in FIG. 25, the concavities andconvexities are formed only in the first face 15 a, and the lightemitting layer 13 is formed as not n concave-convex shape but a flatfilm. In this case, in the same manner as the embodiment mentionedabove, in the semiconductor light emitting device shown in FIG. 25, thelight emitting layer 13 may be formed as n concave-convex shape, so asto achieve an enlargement of an effective light emitting area.

Further, the configuration in which the film having the differentrefraction index from the semiconductor layer 15 such as the AlN film 8or the like is selectively provided in the upper end (the top portion)of the convex portion in the concavities and convexities of the firstface 15 a can be applied to the configuration in FIG. 19A mentionedabove, as shown in FIG. 26A.

Further, the configuration in which the film having the differentrefraction index from the semiconductor layer 15 such as the AlN film 8or the like is selectively provided in the upper end (the top portion)of the convex portion in the concavities and convexities of the firstface 15 a can be applied to the configuration in FIG. 19B mentionedabove, as shown in FIG. 26B. In this case, in FIGS. 26A and 26B, thelight emitting layer 13 may be formed as a concave-convex shape.

After patterning the AlN film 8 in a process shown in FIG. 22C, theresist 94 may be removed as shown in FIG. 23A. Further, thesemiconductor layer 15 can be formed as a concave-convex face as shownin FIG. 23B, for example, in accordance with the RIE using the Cl₂ gas,or the wet process using the KOH, the TMAH or the like, by setting thepatterned AlN film 8 as a mask. In this case, the AlN film 8 can be leftin the upper end (the top portion) of the convex portion in theconcave-convex face of the semiconductor layer 15.

Alternatively, the roughening process (the concave-convexity process) ofthe semiconductor layer 15 can be carried out by utilizing a defect ofthe AlN film 8 without patterning the AlN film 8. In the case that theSiN film, the SiON film, the SiOC film or the SiC film is used as thebuffer layer, it is possible to roughen the semiconductor layer 15 byutilizing the defect of the film.

In other words, as shown in FIG. 24A, the resist is not formed on theAlN film 8, and the AlN film 8 is not patterned. Further, if the wetprocess using the KOH or the TMAH is carried out with respect to the AlNfilm 8, the crystalline anisotropy etching makes progress starting fromthe crystalline defect of the AlN film 8, the semiconductor layer 15 ofthe foundation is etched as shown in FIG. 24B, and the semiconductorlayer 15 is roughened (concave-convexity processed).

Random concavities and convexities corresponding to the defect of theAlN film 8 are formed on the light pickup face of the semiconductorlayer 15. A shape, a size and a repeating pitch of the concavities andconvexities which are formed in the semiconductor layer 15 are atrandom. In this case, the AlN film 8 can be left in the upper end (thetop portion) of the convex portion in the concave-convex face of thesemiconductor layer 15.

In each of the embodiments mentioned above, the p-side interconnectionlayer 21 and the n-side interconnection layer 22 may be bonded to thepad of the mounting substrate, without providing the p-side metal pillar23 and the n-side metal pillar 24.

Further, the p-side interconnection layer 21 and the p-side metal pillar23 are not limited to be the separated bodies, but the p-sideinterconnection portion may be configured by integrally providing thep-side interconnection layer 21 and the p-side metal pillar 23 in thesame process. In the same manner, the n-side interconnection layer 22and the n-side metal pillar 24 are not limited to be the separatedbodies, but the n-side interconnection portion may be configured byintegrally providing the n-side interconnection layer 22 and the n-sidemetal pillar 24 in the same process.

In accordance with the manufacturing method of the semiconductor lightemitting device of the embodiment, the process of forming theconcavities and convexities on the main face of the substrate has aprocess of forming the mask in which the opening is selectively formed,on the main face of the silicon substrate, and a process of crystallineanisotropy etching the silicon substrate using the mask.

Further, in accordance with the manufacturing method of thesemiconductor light emitting device of the embodiment, the main face ofthe silicon substrate is the (100) face, and the (111) face which isinclined with respect to the (100) face is exposed in accordance withthe crystalline anisotropy etching of the (100) face.

Further, in accordance with the manufacturing method of thesemiconductor light emitting device of the embodiment, there areprovided a process of forming the support body in the opposite side tothe substrate, after forming the p-side electrode and the n-sideelectrode, and a process of removing the substrate after forming thesupport body.

Further, in accordance with the manufacturing method of thesemiconductor light emitting device of the embodiment, the process offorming the support body has a process of forming the p-sideinterconnection portion which is electrically connected to the p-sideelectrode, and the n-side interconnection portion which is electricallyconnected to the n-side electrode.

Further, in accordance with the manufacturing method of thesemiconductor light emitting device of the embodiment, the process offorming the support body further has a process of forming the resinlayer between the p-side interconnection portion and the n-sideinterconnection portion.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modification as would fall within the scope andspirit of the inventions.

1-20. (canceled)
 21. A semiconductor light emitting device comprising: asemiconductor layer having a first face having concavities andconvexities, a second face opposite to the first face, and a lightemitting layer; a p-side electrode provided on the semiconductor layer;an n-side electrode provided on the semiconductor layer; a film providedin an upper end of a convex portion of the concavities and convexitiesof the first face, not provided in a concave portion of the concavitiesand convexities of the first face, the film being different in arefraction index from the semiconductor layer; and a resin layerprovided on the first face side.
 22. The device according to claim 21,further comprising: a first insulating film provided on the p-sideelectrode and the n-side electrode, and having a first openingcommunicating with the p-side electrode and a second openingcommunicating with the n-side electrode; a p-side interconnectionportion provided on the first insulating film, and electricallyconnected to the p-side electrode through the first opening; and ann-side interconnection portion provided on the first insulating film,and electrically connected to the n-side electrode through the secondopening.
 23. The device according to claim 22, wherein the firstinsulating film covers a side face that extends from the first face ofthe first nitride semiconductor layer.
 24. The device according to claim22, further comprising a second insulating film provided between thep-side interconnection portion and the n-side interconnection portion.25. The device according to claim 24, wherein the second insulating filmcovers a periphery of the p-side interconnection portion and a peripheryof the n-side interconnection portion.
 26. The device according to claim22, wherein the p-side interconnection portion includes a p-sideinterconnection layer provided inside the first opening and on the firstinsulating film; and a p-side metal pillar provided on the p-sideinterconnection layer and being thicker than the p-side interconnectionlayer, and the n-side interconnection portion includes an n-sideinterconnection layer provided inside the second opening and on thefirst insulating film; and an n-side metal pillar provided on the n-sideinterconnection layer and being thicker than the n-side interconnectionlayer.
 27. The device according to claim 21, wherein the film is abuffer layer.
 28. The device according to claim 27, wherein thesemiconductor layer is a crystal growth layer on a substrate, and thebuffer layer reduces a lattice unconformity.
 29. The device according toclaim 21, wherein the film includes an AlN film.
 30. The deviceaccording to claim 21, wherein the film contains silicon.
 31. The deviceaccording to claim 30, wherein the film containing silicon includes atleast one of a SiN film and a SiON film.
 32. The device according toclaim 30, wherein the film containing silicon includes at least one of aSiOC film and a SiC film.
 33. The device according to claim 21, whereinthe first face has a plurality of films thereon, and lower ends of thefilms are at a same level.
 34. The device according to claim 21, whereinthe surfaces of the concavities and convexities have the same planeorientation.
 35. The device according to claim 34, wherein theconcavities and convexities are crystalline-anisotropic-etched portions.